Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Noble synthesizable hybrid serial-parallel fast multiplier
The purpose of this study was to synthesize the architecture of a fast multiplier using very highspeed integration circuits hardware description language (VHDL). The serial-parallel architecture proposed by Besher, Bourdine, Ashur and Crookes was synthesized by using Altera ModelSim and Quartus II platform. Low latency, most significant bit (MSB) first (online algebra), signed hybrid multiplier architecture is based on three types of adder cells and has a modular structure. The architecture is easy to expand due to the modular structure. Bit serial and MSB first approach resulted in the architecture’s usefulness for image processing math. Use of the redundant numbering system reduced the carry propagation in the audition process. Timing analysis of the synthesized architecture was performed. 2n-digit product output was achieved at every 2n+3 clock cycles. The synthesized multiplier architecture has an average delay of 1.3 ns.
Noble synthesizable hybrid serial-parallel fast multiplier
The purpose of this study was to synthesize the architecture of a fast multiplier using very highspeed integration circuits hardware description language (VHDL). The serial-parallel architecture proposed by Besher, Bourdine, Ashur and Crookes was synthesized by using Altera ModelSim and Quartus II platform. Low latency, most significant bit (MSB) first (online algebra), signed hybrid multiplier architecture is based on three types of adder cells and has a modular structure. The architecture is easy to expand due to the modular structure. Bit serial and MSB first approach resulted in the architecture’s usefulness for image processing math. Use of the redundant numbering system reduced the carry propagation in the audition process. Timing analysis of the synthesized architecture was performed. 2n-digit product output was achieved at every 2n+3 clock cycles. The synthesized multiplier architecture has an average delay of 1.3 ns.
Noble synthesizable hybrid serial-parallel fast multiplier
Deogirikar, Abhijit (Autor:in)
01.05.2016
Sonstige
Elektronische Ressource
Englisch
DDC:
720
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER DESIGN
| BASE | 2019
Continuous path control of a 5-DOF parallel-serial hybrid robot
| British Library Online Contents | 2010
Wire-saving system utilizing serial-parallel transmission
| British Library Online Contents | 1997