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VLSI implementation of a real-time vision based lane departure warning system
Intelligent Vehicle Safety imaging system using image processing often requires a lot of internal memory register or DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) to temporary video and images. But these processes often increases the complexity of the hardware and software. In this system, we propose a VLSI implementation of image-based lane departure warning system. It is not only the gradient calculation of the lines and discrimination out of the lane line, but also real-time analysis of vehicle tires with the left and right side of the lane markings distance through the image of the video, and then judge whether the car lane offsets phenomenon. This system has been implemented in the Xilinx Spartan6 FPGA platform. It is using total 32% of logic resources, and it doesn't use SRAM or SDRAM. Its average recognition rate is 95%, the image frame rate 30 frames / s, and proceed forthwith back-end design with logic synthesis and Auto Place & Rout (APR) processing. This chip uses 0.18 um standard cell process. This system's core area is 1.47 * 1.47 mm2, and core utilization is 0.8, sequential cell occupy 40% and frequency up to 100 MHz. This chip has advantages of low cost, small size and low power more than DSP or FPGA. It will be also more suitable to use in vehicle applications system, without external memory.
VLSI implementation of a real-time vision based lane departure warning system
Intelligent Vehicle Safety imaging system using image processing often requires a lot of internal memory register or DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) to temporary video and images. But these processes often increases the complexity of the hardware and software. In this system, we propose a VLSI implementation of image-based lane departure warning system. It is not only the gradient calculation of the lines and discrimination out of the lane line, but also real-time analysis of vehicle tires with the left and right side of the lane markings distance through the image of the video, and then judge whether the car lane offsets phenomenon. This system has been implemented in the Xilinx Spartan6 FPGA platform. It is using total 32% of logic resources, and it doesn't use SRAM or SDRAM. Its average recognition rate is 95%, the image frame rate 30 frames / s, and proceed forthwith back-end design with logic synthesis and Auto Place & Rout (APR) processing. This chip uses 0.18 um standard cell process. This system's core area is 1.47 * 1.47 mm2, and core utilization is 0.8, sequential cell occupy 40% and frequency up to 100 MHz. This chip has advantages of low cost, small size and low power more than DSP or FPGA. It will be also more suitable to use in vehicle applications system, without external memory.
VLSI implementation of a real-time vision based lane departure warning system
Chang-Kun Yao, (Autor:in) / Yu-Ren Lin, (Autor:in) / Yi-Feng Su, (Autor:in) / Nian-Shiang Chang, (Autor:in)
01.11.2012
959619 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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