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Bottom Contact 100 nm Channel‐Length α‐In2Se3 In‐Plane Ferroelectric Memory
Owing to the emerging trend of non‐volatile memory and data‐centric computing, the demand for more functional materials and efficient device architecture at the nanoscale is becoming stringent. To date, 2D ferroelectrics are cultivated as channel materials in field‐effect transistors for their retentive and switchable dipoles and flexibility to be compacted into diverse structures and integration for intensive production. This study demonstrates the in‐plane (IP) ferroelectric memory effect of a 100 nm channel‐length 2D ferroelectric semiconductor α‐In2Se3 stamped onto nanogap electrodes on Si/SiO2 under a lateral electric field. As α‐In2Se3 forms the bottom contact of the nanogap electrodes, a large memory window of 13 V at drain voltage between ±6.5 V and the on/off ratio reaching 103 can be explained by controlled IP polarization. Furthermore, the memory effect is modulated by the bottom gate voltage of the Si substrate due to the intercorrelation between IP and out‐of‐plane (OOP) polarization. The non‐volatile memory characteristics including stable retention lasting 17 h, and endurance over 1200 cycles suggest a wide range of memory applications utilizing the lateral bottom contact structure.
Bottom Contact 100 nm Channel‐Length α‐In2Se3 In‐Plane Ferroelectric Memory
Owing to the emerging trend of non‐volatile memory and data‐centric computing, the demand for more functional materials and efficient device architecture at the nanoscale is becoming stringent. To date, 2D ferroelectrics are cultivated as channel materials in field‐effect transistors for their retentive and switchable dipoles and flexibility to be compacted into diverse structures and integration for intensive production. This study demonstrates the in‐plane (IP) ferroelectric memory effect of a 100 nm channel‐length 2D ferroelectric semiconductor α‐In2Se3 stamped onto nanogap electrodes on Si/SiO2 under a lateral electric field. As α‐In2Se3 forms the bottom contact of the nanogap electrodes, a large memory window of 13 V at drain voltage between ±6.5 V and the on/off ratio reaching 103 can be explained by controlled IP polarization. Furthermore, the memory effect is modulated by the bottom gate voltage of the Si substrate due to the intercorrelation between IP and out‐of‐plane (OOP) polarization. The non‐volatile memory characteristics including stable retention lasting 17 h, and endurance over 1200 cycles suggest a wide range of memory applications utilizing the lateral bottom contact structure.
Bottom Contact 100 nm Channel‐Length α‐In2Se3 In‐Plane Ferroelectric Memory
Miao, Shurong (Autor:in) / Nitta, Ryosuke (Autor:in) / Izawa, Seiichiro (Autor:in) / Majima, Yutaka (Autor:in)
Advanced Science ; 10
01.10.2023
7 pages
Aufsatz (Zeitschrift)
Elektronische Ressource
Englisch
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