The memory architecture and the cache and memory management unit for the Fairchild CLIPPER processor

Cho, James / Smith, Alan Jay / Sachs, Howard | TIBKAT | 1986

The Review of Cache Partitioning in Multi-Core Processor

Li, S. / Xu, G.C. / Dong, Y.S. et al. | British Library Online Contents | 2010

DDM : a cache-only memory architecture

Hagersten, Erik / Landin, Anders / Haridi, Seif | TIBKAT | 1991

Story, Storage, and Symbol: Functional Cache Architecture, Cache Narratives, and Roadside Attractions

Fair, S. W. / Vernacular Architecture Forum | British Library Conference Proceedings | 1997

Droop Mitigating Last Level Cache Architecture for STTRAM

Aluru, Radha Krishna / Ghosh, Swaroop | British Library Conference Proceedings | 2017