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Compact Reconfigurable Architecture for Sosemanuk Stream Cipher
Sosemanuk is word oriented synchronous stream cipher capable to produce 32 bit ciphertext. It uses variable key from 128 bit to 256 bit and publically known Initialization Vector (IV) of 128 bit. Sosemanuk is one of the finalists in Profile 1 of the eSTREAM Portfolio. This cipher targets to avoid structural properties of SNOW2.0 to improve its efficiency by reducing the internal state size. It also uses reduced round Serpent24 block cipher to provide secure and efficient key loading process. This paper presents compact architecture for Sosemanuk stream cipher. The proposed architecture uses compact S-box architecture and compact modulo adders designed using CLA. The proposed compact S-box minimizes resources utilized without affecting performance. Proposed modulo adder architecture minimizes resources used as compared to conventional CLA implementation. The algorithm was designed by using VHDL language with CAD tool Xilinx ISE design suite 13.2 and implemented on Xilinx Virtex XC5VFX100E FPGA device. The proposed architecture achieved throughput of 4.281 Gbps at clock frequency of 133.788 MHz
Compact Reconfigurable Architecture for Sosemanuk Stream Cipher
Sosemanuk is word oriented synchronous stream cipher capable to produce 32 bit ciphertext. It uses variable key from 128 bit to 256 bit and publically known Initialization Vector (IV) of 128 bit. Sosemanuk is one of the finalists in Profile 1 of the eSTREAM Portfolio. This cipher targets to avoid structural properties of SNOW2.0 to improve its efficiency by reducing the internal state size. It also uses reduced round Serpent24 block cipher to provide secure and efficient key loading process. This paper presents compact architecture for Sosemanuk stream cipher. The proposed architecture uses compact S-box architecture and compact modulo adders designed using CLA. The proposed compact S-box minimizes resources utilized without affecting performance. Proposed modulo adder architecture minimizes resources used as compared to conventional CLA implementation. The algorithm was designed by using VHDL language with CAD tool Xilinx ISE design suite 13.2 and implemented on Xilinx Virtex XC5VFX100E FPGA device. The proposed architecture achieved throughput of 4.281 Gbps at clock frequency of 133.788 MHz
Compact Reconfigurable Architecture for Sosemanuk Stream Cipher
Nagnath B. Hulle (author) / Prathiba B (author) / Sarika R Khope (author) / Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP)
2020-02-29
oai:zenodo.org:5568753
International Journal of Engineering and Advanced Technology (IJEAT) 9(3) 607-611
Article (Journal)
Electronic Resource
English
modulo adders , Sosemanuk , Retrieval Number , Stream Cipher , ISSN , Compact , FPGA
DDC:
720