A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
A "neural-RISC" processor and parallel architecture for neural networks
This thesis investigates a RISC microprocessor and a parallel architecture designed to optimise the computation of neural network models. The "Neural-RISC" is a primitive transputer-like microprocessor for building a parallel MIMD (multiple instruction, multiple data) general-purpose neurocomputer. The thesis covers four major parts: the design of the Neural-RISC system architecture, the design of the Neural-RISC node architecture, the architecture simulation studies, and the VLSI implementation of a microchip prototype. The Neural-RISC system architecture consists of linear arrays of microprocessors connected in rings. Rings end up in an interconnecting module forming a cluster. Clusters of rings are arranged in different point-to-point topologies and are controlled by a host computer. The interconnect module in each cluster acts as a communications server supporting inter-ring and inter-cluster message routing. The host, which consists of a workstation, supports network initialisation, programming and monitoring. During operation, messages in the form of packets can address: a node, a distinct group of nodes (cf. a neural network layer or cluster), all nodes (cf. broadcast), or the host. The neurocomputer nodes are configurated by downloading simple programs into each microprocessor. The Neural-RISC node architecture comprises a 16-bit reduced instruction-set processor, a communication unit, and local memory-all integrated into the same silicon die. The processor employs 16 instructions: 11 execute in one cycle; 4 in two cycles, and the multiply instruction executes in 16 cycles. One expanding opcode branches into a set of single-cycle, memory-mapped instructions. The communication unit provides four (unidirectional) point-to-point 16-bit links and a simple protocol for routing packets. Local memory contains: a RAM memory for instructions and data; two variable length FIFO buffers (as part of the working memory) to support the communication links; and a bootstrapping ROM. The architecture simulation studies ...
A "neural-RISC" processor and parallel architecture for neural networks
This thesis investigates a RISC microprocessor and a parallel architecture designed to optimise the computation of neural network models. The "Neural-RISC" is a primitive transputer-like microprocessor for building a parallel MIMD (multiple instruction, multiple data) general-purpose neurocomputer. The thesis covers four major parts: the design of the Neural-RISC system architecture, the design of the Neural-RISC node architecture, the architecture simulation studies, and the VLSI implementation of a microchip prototype. The Neural-RISC system architecture consists of linear arrays of microprocessors connected in rings. Rings end up in an interconnecting module forming a cluster. Clusters of rings are arranged in different point-to-point topologies and are controlled by a host computer. The interconnect module in each cluster acts as a communications server supporting inter-ring and inter-cluster message routing. The host, which consists of a workstation, supports network initialisation, programming and monitoring. During operation, messages in the form of packets can address: a node, a distinct group of nodes (cf. a neural network layer or cluster), all nodes (cf. broadcast), or the host. The neurocomputer nodes are configurated by downloading simple programs into each microprocessor. The Neural-RISC node architecture comprises a 16-bit reduced instruction-set processor, a communication unit, and local memory-all integrated into the same silicon die. The processor employs 16 instructions: 11 execute in one cycle; 4 in two cycles, and the multiply instruction executes in 16 cycles. One expanding opcode branches into a set of single-cycle, memory-mapped instructions. The communication unit provides four (unidirectional) point-to-point 16-bit links and a simple protocol for routing packets. Local memory contains: a RAM memory for instructions and data; two variable length FIFO buffers (as part of the working memory) to support the communication links; and a bootstrapping ROM. The architecture simulation studies ...
A "neural-RISC" processor and parallel architecture for neural networks
Pacheco, Marco Aurelio Cavalcanti (author)
1991-01-01
Doctoral thesis, UCL (University College London).
Theses
Electronic Resource
English
DDC:
720
Securing a RISC-V Architecture: A Dynamic Approach
| British Library Conference Proceedings | 2023
Parallel Processing, Neural Networks and Genetic Algorithms: Revisited
| British Library Conference Proceedings | 1996
3D Graph Convolutional Neural Networks in Architecture Design
| TIBKAT | 2021
Subdomain Generation Using Parallel Q-State Potts Neural Networks
| British Library Conference Proceedings | 1995