A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
Data speculative multithreaded architecture
We present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dependences, the relatively small window size and the instruction fetch bandwidth. The new architecture executes simultaneously multiple threads of control obtained from a single program by means of control speculation techniques that do not require any compiler/user support nor any special feature in the instruction set architecture. The multiple simultaneous threads execute different iterations of the same loop, which require the same fetch bandwidth as a single thread since they share the same code. Inter-thread dependences as well as the values that flow through them are speculated by means of data prediction techniques. The preliminary evaluation results show a significant speed-up when compared with a superscalar processor. In fact, the new processor architecture can achieve an IPC (instructions per cycle) rate even larger than the peak fetch bandwidth ; Peer Reviewed ; Postprint (published version)
Data speculative multithreaded architecture
We present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dependences, the relatively small window size and the instruction fetch bandwidth. The new architecture executes simultaneously multiple threads of control obtained from a single program by means of control speculation techniques that do not require any compiler/user support nor any special feature in the instruction set architecture. The multiple simultaneous threads execute different iterations of the same loop, which require the same fetch bandwidth as a single thread since they share the same code. Inter-thread dependences as well as the values that flow through them are speculated by means of data prediction techniques. The preliminary evaluation results show a significant speed-up when compared with a superscalar processor. In fact, the new processor architecture can achieve an IPC (instructions per cycle) rate even larger than the peak fetch bandwidth ; Peer Reviewed ; Postprint (published version)
Data speculative multithreaded architecture
1998-01-01
Miscellaneous
Electronic Resource
English
DDC:
720
Execution architecture of the multithreaded ADAM prototype
| UB Braunschweig | 1996
Execution architecture of the multithreaded ADAM prototype
| UB Braunschweig | 1996
Execution architecture of the multithreaded ADAM prototype
| TIBKAT | 1996