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Comparing Admission Control Architectures for Real-Time Ethernet
Industry 4.0 and Autonomous Driving are emerging resource-intensive distributed application domains that deal with open and evolving environments. These systems are subject to stringent resource, timing, and other non-functional constraints, as well as frequent reconfiguration. Thus, real-time behavior must not preclude operational flexibility. This combination is motivating ongoing efforts within the Time Sensitive Networking (TSN) standardization committee to define admission control mechanisms for Ethernet. Existing mechanisms in TSN, like those of AVB, its predecessor, follow a distributed architecture that favors scalability. Conversely, the new mechanisms envisaged for TSN (IEEE 802.1Qcc) follow a (partially) centralized architecture, favoring short reconfiguration latency. This paper shows the first quantitative comparison between distributed and centralized admission control architectures concerning reconfiguration latency. Here, we compare AVB against a dynamic real-time reconfigurable Ethernet technology with centralized management, namely HaRTES. Our experiments show a significantly lower latency using the centralized architecture. We also observe the dependence of the distributed architecture in the end nodes' performance and the benefit of having a protected channel for the admission control transactions. ; This work was supported in part by the Spanish Agencia Estatal de Investigación (AEI), in part by the Fondo Europeo de Desarrollo Regional (FEDER) [AEI/FEDER, Unión Europea (UE)] under Grant TEC2015-70313-R, in part by the European Regional Development Fund (FEDER) through the Operational Programme for Competitivity and the Internationalization of Portugal 2020 Partnership Agreement (PRODUTECH-SIF) under Grant POCI-01-0247-FEDER-024541, and in part by the Research Centre Instituto de Telecomunicações under Grant UID/EEA/50008/2013. ; info:eu-repo/semantics/publishedVersion
Comparing Admission Control Architectures for Real-Time Ethernet
Industry 4.0 and Autonomous Driving are emerging resource-intensive distributed application domains that deal with open and evolving environments. These systems are subject to stringent resource, timing, and other non-functional constraints, as well as frequent reconfiguration. Thus, real-time behavior must not preclude operational flexibility. This combination is motivating ongoing efforts within the Time Sensitive Networking (TSN) standardization committee to define admission control mechanisms for Ethernet. Existing mechanisms in TSN, like those of AVB, its predecessor, follow a distributed architecture that favors scalability. Conversely, the new mechanisms envisaged for TSN (IEEE 802.1Qcc) follow a (partially) centralized architecture, favoring short reconfiguration latency. This paper shows the first quantitative comparison between distributed and centralized admission control architectures concerning reconfiguration latency. Here, we compare AVB against a dynamic real-time reconfigurable Ethernet technology with centralized management, namely HaRTES. Our experiments show a significantly lower latency using the centralized architecture. We also observe the dependence of the distributed architecture in the end nodes' performance and the benefit of having a protected channel for the admission control transactions. ; This work was supported in part by the Spanish Agencia Estatal de Investigación (AEI), in part by the Fondo Europeo de Desarrollo Regional (FEDER) [AEI/FEDER, Unión Europea (UE)] under Grant TEC2015-70313-R, in part by the European Regional Development Fund (FEDER) through the Operational Programme for Competitivity and the Internationalization of Portugal 2020 Partnership Agreement (PRODUTECH-SIF) under Grant POCI-01-0247-FEDER-024541, and in part by the Research Centre Instituto de Telecomunicações under Grant UID/EEA/50008/2013. ; info:eu-repo/semantics/publishedVersion
Comparing Admission Control Architectures for Real-Time Ethernet
Alvarez, Ines (author) / Moutinho, Luis (author) / Pedreiras, Paulo (author) / Bujosa, Daniel (author) / Proenza, Julian (author) / Almeida, Luis (author)
2020-01-01
doi:10.1109/ACCESS.2020.2999817
Article (Journal)
Electronic Resource
English
DDC:
720
Parallel architectures for real-time control
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