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HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations
This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.
HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations
This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.
HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations
Awab, Ainy Haziyah (author) / Ab Rahman, Ab Al-Hadi (author) / Rusli, Mohd Shahrizal (author) / Sheikh, Usman Ullah (author) / Kamisian, Izam (author) / Meng, Goh Kam (author)
2019-10-01
doi:10.12928/telkomnika.v17i5.12815
TELKOMNIKA (Telecommunication Computing Electronics and Control); Vol 17, No 5: October 2019; 2457-2464 ; 2302-9293 ; 1693-6930 ; 10.12928/telkomnika.v17i5
Article (Journal)
Electronic Resource
English
ASIC , low energy , HEVC , FPGA , DCT
DDC:
720
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