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POLYCRYSTAL CERAMIC SUBSTRATE, POLYCRYSTAL CERAMIC SUBSTRATE WITH JOINT LAYER AND LAMINATE SUBSTRATE
PROBLEM TO BE SOLVED: To provide a polycrystal ceramic substrate suitable as a ground substrate of a laminate substrate capable of suppressing reduction of manufacturing efficiency of a semiconductor device due to deterioration of a joint state, a polycrystal ceramic substrate with a joint layer containing the polycrystal ceramic substrate and a laminate substrate.SOLUTION: There is provided a polycrystal ceramic substrate 10 jointed to a compound semiconductor substrate 30 via a joint layer 20, and satisfying at least one of Relational expression (1) 0.7<α/α<0.9 (1) and Relational expression (2) 0.7<α/α<0.9 (2), where αis linear expansion coefficient of the polycrystal ceramic substrate 10 and αis linear expansion coefficient of the compound semiconductor substrate 30, at 30°C to 300°C, αis linear expansion coefficient of the polycrystal ceramic substrate 10 and αis linear expansion coefficient of the compound semiconductor substrate 30, at 30°C to 1000°C.SELECTED DRAWING: Figure 1
【課題】接合状態の悪化に起因する半導体装置の製造効率の低下を抑制することが可能な積層基板の下地基板として好適な多結晶セラミック基板、当該多結晶セラミック基板を含む接合層付き多結晶セラミック基板および積層基板の提供。【解決手段】化合物半導体基板３０に対して接合層２０を介して接合される多結晶セラミック基板１０において、３０℃〜３００℃における、多結晶セラミック基板１０の線膨張係数をα１、化合物半導体基板３０の線膨張係数をα２とし、３０℃〜１０００℃における、多結晶セラミック基板１０の線膨張係数をα３、化合物半導体基板３０の線膨張係数をα４とした場合に、関係式（１）０．７＜α１／α２＜０．９・・・（１）および関係式（２）０．７＜α３／α４＜０．９・・・（２）のうち少なくともいずれか一方が成立する、多結晶セラミック基板１０。【選択図】図１
POLYCRYSTAL CERAMIC SUBSTRATE, POLYCRYSTAL CERAMIC SUBSTRATE WITH JOINT LAYER AND LAMINATE SUBSTRATE
PROBLEM TO BE SOLVED: To provide a polycrystal ceramic substrate suitable as a ground substrate of a laminate substrate capable of suppressing reduction of manufacturing efficiency of a semiconductor device due to deterioration of a joint state, a polycrystal ceramic substrate with a joint layer containing the polycrystal ceramic substrate and a laminate substrate.SOLUTION: There is provided a polycrystal ceramic substrate 10 jointed to a compound semiconductor substrate 30 via a joint layer 20, and satisfying at least one of Relational expression (1) 0.7<α/α<0.9 (1) and Relational expression (2) 0.7<α/α<0.9 (2), where αis linear expansion coefficient of the polycrystal ceramic substrate 10 and αis linear expansion coefficient of the compound semiconductor substrate 30, at 30°C to 300°C, αis linear expansion coefficient of the polycrystal ceramic substrate 10 and αis linear expansion coefficient of the compound semiconductor substrate 30, at 30°C to 1000°C.SELECTED DRAWING: Figure 1
【課題】接合状態の悪化に起因する半導体装置の製造効率の低下を抑制することが可能な積層基板の下地基板として好適な多結晶セラミック基板、当該多結晶セラミック基板を含む接合層付き多結晶セラミック基板および積層基板の提供。【解決手段】化合物半導体基板３０に対して接合層２０を介して接合される多結晶セラミック基板１０において、３０℃〜３００℃における、多結晶セラミック基板１０の線膨張係数をα１、化合物半導体基板３０の線膨張係数をα２とし、３０℃〜１０００℃における、多結晶セラミック基板１０の線膨張係数をα３、化合物半導体基板３０の線膨張係数をα４とした場合に、関係式（１）０．７＜α１／α２＜０．９・・・（１）および関係式（２）０．７＜α３／α４＜０．９・・・（２）のうち少なくともいずれか一方が成立する、多結晶セラミック基板１０。【選択図】図１
POLYCRYSTAL CERAMIC SUBSTRATE, POLYCRYSTAL CERAMIC SUBSTRATE WITH JOINT LAYER AND LAMINATE SUBSTRATE
多結晶セラミック基板、接合層付き多結晶セラミック基板および積層基板
SHIMOJI KEIICHIRO (author) / NAKAYAMA SHIGERU (author) / YOSHIMURA MASASHI (author)
2017-10-12
Patent
Electronic Resource
Japanese
COMPOSITE POLYCRYSTAL AND TOOL WITH COMPOSITE POLYCRYSTAL
| European Patent Office | 2024