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Stepped segment LFSR for low test power BIST
The power during testing is very greater than the functional power in the BIST which affects the reliability of the chip and it is due to the less correlation between the test patterns generated by TPG. In this paper a new low transition TPG is proposed which allows maximum 2 transitions between the consecutive test patterns by stepped segment activation of LFSR. From the experiments conducted on ISCAS'89 benchmark circuits the proposed LFSR reduces the testing power averagely by 19.63% with little reduction in fault coverage.
Stepped segment LFSR for low test power BIST
The power during testing is very greater than the functional power in the BIST which affects the reliability of the chip and it is due to the less correlation between the test patterns generated by TPG. In this paper a new low transition TPG is proposed which allows maximum 2 transitions between the consecutive test patterns by stepped segment activation of LFSR. From the experiments conducted on ISCAS'89 benchmark circuits the proposed LFSR reduces the testing power averagely by 19.63% with little reduction in fault coverage.
Stepped segment LFSR for low test power BIST
Ram, B.V. Bhargav (author) / Harish, G. (author) / Yelampalli, Shiva (author)
2015-05-01
313167 byte
Conference paper
Electronic Resource
English
| IEEE | 2015
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