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Partial Sum Based Algorithm for the Discrete Cosine Transform
In this paper, a fast algorithm and its corresponding hardware structure are developed for the 2M x 2M type Discrete Cosine Transform. The transform output is transformed into a mul-add format by the definition of the 2-D DCT/IDCT. The output data set is partitioned into several subsets each having the same multiplicands that we call partial sum. By computing partial sum, the addition and multiplication operation times can be greatly reduced. In final, its corresponding hardware architecture is presented for VLSI implementation. The synthesis result shows that the algorithm is efficient and reliable.
Partial Sum Based Algorithm for the Discrete Cosine Transform
In this paper, a fast algorithm and its corresponding hardware structure are developed for the 2M x 2M type Discrete Cosine Transform. The transform output is transformed into a mul-add format by the definition of the 2-D DCT/IDCT. The output data set is partitioned into several subsets each having the same multiplicands that we call partial sum. By computing partial sum, the addition and multiplication operation times can be greatly reduced. In final, its corresponding hardware architecture is presented for VLSI implementation. The synthesis result shows that the algorithm is efficient and reliable.
Partial Sum Based Algorithm for the Discrete Cosine Transform
Tian, Mao (author) / Li, Guang-jun (author) / Peng, Qi-zong (author)
2006-06-01
4029032 byte
Conference paper
Electronic Resource
English
| Taylor & Francis Verlag | 2023
| British Library Online Contents | 2016