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Architectures for finite Radon transform
Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.
Architectures for finite Radon transform
Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.
Architectures for finite Radon transform
Rahman, C.A. (author) / Badawy, W. (author)
2004-07-22
2 pages
Article (Journal)
English
82 MHz , finite Radon transform , reference architecture , image resolution , parallel architectures , integrated logic circuits , memoryless architecture , 100 MHz , CIF image sequence processing , image blocks , memoryless systems , VLSI architectures , Radon transforms , VLSI , memory blocks , image sequences
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