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Modern Design and Testing of High Speed Vedic ALU Controller using Vedic Algorithms
https://orcid.org/http://orcid.org/0000-0002-4602-6324
Nowadays system to other Hardware Components Connectivity is growing rapidly for many Logical operations, with the increase in Connectivity, Complexity of hardware and increase in power utility. For any computing System main heart of work depends on central processing unit in which logic is developed with standard Arithmetic Logic Units (ALU’s), performance of ALU increases the chances of higher efficiency throughput. The authors proposed a new Vedic ALU Controller for high-speed performance in which many operations are used, commonly a 32bit Reversible Vedic Multiplier using Urdhva Tiryakbhyam Algorithm and a 32 bit Reversible Vedic Squarer blocks using Ekadhikina Purvena Algorithm are included with Arithmetic and Logical operations, which are implemented using Reversible Logic Fredkin Gate. The Controller makes use of less area when not in use and also utilizes the power for many applications (50% operations are used and rest are unused), controlling the ALU proportional to the control of power utilized for the system. Two algorithms are developed which are used for testing the Multiplier using Ekadhikina Purvena Algorithm and Squarer Circuits using Vedic Yaavadunam Algorithm for output results and simulated successfully. In this proposed work, compared to conventional Multiplier designs, there is 25% reduction in an area and slight variation in output efficiency by 80% higher. The results are carried out by using Synopsys VCS tool and also Xilinx ISE 14.7, using Verilog HDL.
Modern Design and Testing of High Speed Vedic ALU Controller using Vedic Algorithms
https://orcid.org/http://orcid.org/0000-0002-4602-6324
Nowadays system to other Hardware Components Connectivity is growing rapidly for many Logical operations, with the increase in Connectivity, Complexity of hardware and increase in power utility. For any computing System main heart of work depends on central processing unit in which logic is developed with standard Arithmetic Logic Units (ALU’s), performance of ALU increases the chances of higher efficiency throughput. The authors proposed a new Vedic ALU Controller for high-speed performance in which many operations are used, commonly a 32bit Reversible Vedic Multiplier using Urdhva Tiryakbhyam Algorithm and a 32 bit Reversible Vedic Squarer blocks using Ekadhikina Purvena Algorithm are included with Arithmetic and Logical operations, which are implemented using Reversible Logic Fredkin Gate. The Controller makes use of less area when not in use and also utilizes the power for many applications (50% operations are used and rest are unused), controlling the ALU proportional to the control of power utilized for the system. Two algorithms are developed which are used for testing the Multiplier using Ekadhikina Purvena Algorithm and Squarer Circuits using Vedic Yaavadunam Algorithm for output results and simulated successfully. In this proposed work, compared to conventional Multiplier designs, there is 25% reduction in an area and slight variation in output efficiency by 80% higher. The results are carried out by using Synopsys VCS tool and also Xilinx ISE 14.7, using Verilog HDL.
Modern Design and Testing of High Speed Vedic ALU Controller using Vedic Algorithms
https://orcid.org/http://orcid.org/0000-0002-4602-6324
Nowadays system to other Hardware Components Connectivity is growing rapidly for many Logical operations, with the increase in Connectivity, Complexity of hardware and increase in power utility. For any computing System main heart of work depends on central processing unit in which logic is developed with standard Arithmetic Logic Units (ALU’s), performance of ALU increases the chances of higher efficiency throughput. The authors proposed a new Vedic ALU Controller for high-speed performance in which many operations are used, commonly a 32bit Reversible Vedic Multiplier using Urdhva Tiryakbhyam Algorithm and a 32 bit Reversible Vedic Squarer blocks using Ekadhikina Purvena Algorithm are included with Arithmetic and Logical operations, which are implemented using Reversible Logic Fredkin Gate. The Controller makes use of less area when not in use and also utilizes the power for many applications (50% operations are used and rest are unused), controlling the ALU proportional to the control of power utilized for the system. Two algorithms are developed which are used for testing the Multiplier using Ekadhikina Purvena Algorithm and Squarer Circuits using Vedic Yaavadunam Algorithm for output results and simulated successfully. In this proposed work, compared to conventional Multiplier designs, there is 25% reduction in an area and slight variation in output efficiency by 80% higher. The results are carried out by using Synopsys VCS tool and also Xilinx ISE 14.7, using Verilog HDL.
Modern Design and Testing of High Speed Vedic ALU Controller using Vedic Algorithms
J. Inst. Eng. India Ser. B
Rayudu, K. V. B. V. (author) / Jahagirdar, D. R. (author) / Rao, P. Srihari (author)
Journal of The Institution of Engineers (India): Series B ; 104 ; 221-230
2023-02-01
10 pages
Article (Journal)
Electronic Resource
English
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