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An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Abstract The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Abstract The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Biswas, Baishik (author) / Mukherjee, Rohan (author) / Saha, Priyabrata (author) / Chakrabarti, Indrajit (author)
Journal of The Institution of Engineers (India): Series B ; 97 ; 303-309
2015-02-20
7 pages
Article (Journal)
Electronic Resource
English
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