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A Novel Multilevel Inverter with Reduced Number of Switches Using Simplified PWM Technique
https://orcid.org/http://orcid.org/0000-0003-0614-3654
Multilevel inverter (MLI) topologies greatly sustained the emergence of modish power-electronic device as an expressive substitute of traditional two-level inverters in the area of medium-voltage high-power energy conversion schemes. It recommends the most outstanding solutions for high-power applications particularly in distributed generation schemes and plays a key role for establishment of novel MLI structures with fewer switching components. This paper proposes the novel 7-level asymmetric MLI topology and administered by both fundamental frequency-based pulse-width modulation (PWM) scheme and advanced multi-carrier PWM scheme. The proposed asymmetric 7-level smart MLI topology offers low switching elements, low gate drive circuits, low cost, minimum space requirement, low-voltage dv/dt switch stress, low switching loss and high efficiency over the traditional topologies. The critical evaluation of proposed 7-level asymmetric MLI performance is verified by MATLAB/Simulink platform and validated through experimental prototype; results are illustrated with proper comparisons.
A Novel Multilevel Inverter with Reduced Number of Switches Using Simplified PWM Technique
https://orcid.org/http://orcid.org/0000-0003-0614-3654
Multilevel inverter (MLI) topologies greatly sustained the emergence of modish power-electronic device as an expressive substitute of traditional two-level inverters in the area of medium-voltage high-power energy conversion schemes. It recommends the most outstanding solutions for high-power applications particularly in distributed generation schemes and plays a key role for establishment of novel MLI structures with fewer switching components. This paper proposes the novel 7-level asymmetric MLI topology and administered by both fundamental frequency-based pulse-width modulation (PWM) scheme and advanced multi-carrier PWM scheme. The proposed asymmetric 7-level smart MLI topology offers low switching elements, low gate drive circuits, low cost, minimum space requirement, low-voltage dv/dt switch stress, low switching loss and high efficiency over the traditional topologies. The critical evaluation of proposed 7-level asymmetric MLI performance is verified by MATLAB/Simulink platform and validated through experimental prototype; results are illustrated with proper comparisons.
A Novel Multilevel Inverter with Reduced Number of Switches Using Simplified PWM Technique
https://orcid.org/http://orcid.org/0000-0003-0614-3654
Multilevel inverter (MLI) topologies greatly sustained the emergence of modish power-electronic device as an expressive substitute of traditional two-level inverters in the area of medium-voltage high-power energy conversion schemes. It recommends the most outstanding solutions for high-power applications particularly in distributed generation schemes and plays a key role for establishment of novel MLI structures with fewer switching components. This paper proposes the novel 7-level asymmetric MLI topology and administered by both fundamental frequency-based pulse-width modulation (PWM) scheme and advanced multi-carrier PWM scheme. The proposed asymmetric 7-level smart MLI topology offers low switching elements, low gate drive circuits, low cost, minimum space requirement, low-voltage dv/dt switch stress, low switching loss and high efficiency over the traditional topologies. The critical evaluation of proposed 7-level asymmetric MLI performance is verified by MATLAB/Simulink platform and validated through experimental prototype; results are illustrated with proper comparisons.
A Novel Multilevel Inverter with Reduced Number of Switches Using Simplified PWM Technique
J. Inst. Eng. India Ser. B
Chavali, Punya Sekhar (author) / Rao, P. V. Ramana (author) / Vani, M. Uma (author)
Journal of The Institution of Engineers (India): Series B ; 101 ; 203-216
2020-06-01
14 pages
Article (Journal)
Electronic Resource
English
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