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Interconnect Design Challenges in Nano CMOS Circuit
Interconnect Design Challenges in Nano CMOS Circuit
Interconnect Design Challenges in Nano CMOS Circuit
Masu, K. (Autor:in) / Amakawa, S. (Autor:in) / Ito, H. (Autor:in) / Ishihara, N. (Autor:in) / Miyazaki, S. / Tabata, H.
01.01.2011
7 pages
Aufsatz (Zeitschrift)
Englisch
DDC:
620.11
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