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Interconnect Design Challenges in Nano CMOS Circuit

Masu, K. / Amakawa, S. / Ito, H. / Ishihara, N.

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Interconnect Design Challenges in Nano CMOS Circuit

Masu, K. / Amakawa, S. / Ito, H. / Ishihara, N.

Interconnect Design Challenges in Nano CMOS Circuit

Masu, K. / Amakawa, S. / Ito, H. / Ishihara, N.

Access

Access via TIB

Check availability in my library

Order at Subito €

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Document information

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Document information

Title:

Interconnect Design Challenges in Nano CMOS Circuit

Contributors:

Masu, K. (author) / Amakawa, S. (author) / Ito, H. (author) / Ishihara, N. (author) / Miyazaki, S. / Tabata, H.

Published in:

Technology Evolution for Silicon Nano-Electronics ; 224-230

KEY ENGINEERING MATERIALS ; 470

Publication date:

2011-01-01

Size:

7 pages

ISSN:

1013-9826

Type of media:

Article (Journal)

Type of material:

Language:

English

Classification:

DDC: 620.11

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