Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Preparation method of high-compactness zinc oxide piezoresistor chip
The invention relates to the technical field of piezoresistors, and particularly discloses a preparation method of a high-compactness zinc oxide piezoresistor chip, which comprises the following steps: S1, carrying out primary mixed grinding, S2, carrying out secondary mixed grinding, S3, carrying out continuous ball milling, and S4, spraying, drying, granulating, discharging glue, sintering, annealing, carrying out reduction treatment, applying insulating glaze to the upper side surface, welding a copper wire electrode, vulcanizing and curing to obtain the piezoresistor chip. According to thehigh-compactness zinc oxide piezoresistor chip disclosed by the invention, the uniformity and compactness of the zinc oxide piezoresistor can be improved, so that the zinc oxide piezoresistor is noteasy to thermally collapse and damage during working, in addition, the preparation method has the advantages of being simple, easy to operate and wide in application range.
本申请涉及压敏电阻的技术领域，具体公开了一种高致密性氧化锌压敏电阻芯片的制备方法，包括以下步骤：S1、一次混磨；S2、二次混磨；S3、续球磨；S4、喷雾、干燥、造粒、排胶、烧结、退火、还原处理、上侧面绝缘釉、焊接铜导线电极、硫化和固化，制得压敏电阻芯片。本申请的高致密性氧化锌压敏电阻芯片可增加氧化锌压敏电阻的均匀性和致密性，使氧化锌压敏电阻在工作时不易热崩溃损坏；另外，申请的制备方法具有简单易操作，应用范围广泛的优点。
Preparation method of high-compactness zinc oxide piezoresistor chip
The invention relates to the technical field of piezoresistors, and particularly discloses a preparation method of a high-compactness zinc oxide piezoresistor chip, which comprises the following steps: S1, carrying out primary mixed grinding, S2, carrying out secondary mixed grinding, S3, carrying out continuous ball milling, and S4, spraying, drying, granulating, discharging glue, sintering, annealing, carrying out reduction treatment, applying insulating glaze to the upper side surface, welding a copper wire electrode, vulcanizing and curing to obtain the piezoresistor chip. According to thehigh-compactness zinc oxide piezoresistor chip disclosed by the invention, the uniformity and compactness of the zinc oxide piezoresistor can be improved, so that the zinc oxide piezoresistor is noteasy to thermally collapse and damage during working, in addition, the preparation method has the advantages of being simple, easy to operate and wide in application range.
本申请涉及压敏电阻的技术领域，具体公开了一种高致密性氧化锌压敏电阻芯片的制备方法，包括以下步骤：S1、一次混磨；S2、二次混磨；S3、续球磨；S4、喷雾、干燥、造粒、排胶、烧结、退火、还原处理、上侧面绝缘釉、焊接铜导线电极、硫化和固化，制得压敏电阻芯片。本申请的高致密性氧化锌压敏电阻芯片可增加氧化锌压敏电阻的均匀性和致密性，使氧化锌压敏电阻在工作时不易热崩溃损坏；另外，申请的制备方法具有简单易操作，应用范围广泛的优点。
Preparation method of high-compactness zinc oxide piezoresistor chip
一种高致密性氧化锌压敏电阻芯片的制备方法
ZHANG QI (Autor:in) / SHI GUONENG (Autor:in) / YUE TAO (Autor:in) / FENG ZHIWEI (Autor:in)
09.03.2021
Patent
Elektronische Ressource
Chinesisch
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