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Breakdown voltage reduction in I-MOS devices
Four-stage strategy has been confirmed to reduce the breakdown voltage of 70-nm impact-ionization MOS (I-MOS) devices. Simulation results showed that it was difficult to reduce the breakdown voltage below -5 V only by scaling down some device parameters such as LI, xj,se, and tox. Thus, a strained SOI (SSOI) substrate is introduced which has narrow EG. Though it consists of pure silicon, when strain is maximized, it is observed that the breakdown voltage reaches -1.25 V, which is much lower than that of GOI substrate.
Breakdown voltage reduction in I-MOS devices
Four-stage strategy has been confirmed to reduce the breakdown voltage of 70-nm impact-ionization MOS (I-MOS) devices. Simulation results showed that it was difficult to reduce the breakdown voltage below -5 V only by scaling down some device parameters such as LI, xj,se, and tox. Thus, a strained SOI (SSOI) substrate is introduced which has narrow EG. Though it consists of pure silicon, when strain is maximized, it is observed that the breakdown voltage reaches -1.25 V, which is much lower than that of GOI substrate.
Breakdown voltage reduction in I-MOS devices
Woo Young Choi, (Autor:in) / Jae Young Song, (Autor:in) / Jong Pil Kim, (Autor:in) / Sang Wan Kim, (Autor:in) / Jong Duk Lee, (Autor:in) / Byung-Gook Park, (Autor:in)
01.10.2006
304844 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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