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Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs
We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.
Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs
We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.
Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs
Ma, X. (Autor:in) / Huang, J. (Autor:in) / Chiminazzo, F. (Autor:in) / Rossi, D. (Autor:in) / Metra, C. (Autor:in) / Lombardi, F. (Autor:in)
01.09.2008
556355 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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