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Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs

Ma, X. / Huang, J. / Chiminazzo, F. / Rossi, D. / Metra, C. / Lombardi, F.

We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.

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Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs

Ma, X. / Huang, J. / Chiminazzo, F. / Rossi, D. / Metra, C. / Lombardi, F.

We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.

Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs

Ma, X. / Huang, J. / Chiminazzo, F. / Rossi, D. / Metra, C. / Lombardi, F.

We present a detailed treatment of Crossbar Switching Networks (R-CSNs) made of resistive elements for memory utilization (as look-up table) in a nano FPGA. Initially, a technology assessment of this technology compared with a VLSI CMOS based memory is pursued considering area and support circuitry. Then, a graph model is utilized for characterizing the effects of a single fault on the fault tolerant capabilities of a R-CSN. This is used to establish the exact analytical expression for the fault tolerance of a R-CSN in the presence of a single stuck-open/closed fault. The presented analysis confirms that small-sized R-CSNs are well suited as LUTs for FPGAs at nano scales.

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Title:

Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs

Contributors:

Ma, X. (author) / Huang, J. (author) / Chiminazzo, F. (author) / Rossi, D. (author) / Metra, C. (author) / Lombardi, F. (author)

Published in:

2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems ; 21-24

Publication date:

2008-09-01

Size:

556355 byte

ISBN:

978-0-7695-3379-7

DOI:

https://doi.org/10.1109/NDCS.2008.21

Type of media:

Conference paper

Type of material:

Electronic Resource

Language:

English

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