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Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Hardware realization of concise evolutionary algorithm on FPEA
Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard concise evolutionary algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for realization, the architecture processing speed and the solving power of the CEA for Evolutionary Hardware.
Hardware realization of concise evolutionary algorithm on FPEA
Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard concise evolutionary algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for realization, the architecture processing speed and the solving power of the CEA for Evolutionary Hardware.
Hardware realization of concise evolutionary algorithm on FPEA
Shengli Yan, (Autor:in) / Yue Chen, (Autor:in) / Qingmin Pu, (Autor:in)
01.11.2009
84876 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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