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Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network
This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.
Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network
This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.
Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network
Ilghar Rezaei (author) / Ali Soldoozy (author) / Amir Ali Mohammad Khani (author) / Ali Biabanifard (author)
2023
Article (Journal)
Electronic Resource
Unknown
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