A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell
A vertical channel Nanoscale MOSFET for low leakage Dynamic Random Access Memory (DRAM) cell is proposed. Due to longer channel length than that of the conventional planner structure, the vertical channel structure can dramatically reduce short channel effect (SCE). This structure features a source extension to enhance subthreshold swing (SS), and a neck sidewall spacer to reduce gate induced drain leakage (GIDL).
Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell
A vertical channel Nanoscale MOSFET for low leakage Dynamic Random Access Memory (DRAM) cell is proposed. Due to longer channel length than that of the conventional planner structure, the vertical channel structure can dramatically reduce short channel effect (SCE). This structure features a source extension to enhance subthreshold swing (SS), and a neck sidewall spacer to reduce gate induced drain leakage (GIDL).
Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell
Seung-Hyun Song, (author) / Jeong-Soo Lee, (author) / Yoon-Ha Jeong, (author)
2006-10-01
284944 byte
Conference paper
Electronic Resource
English
A Nanoscale Look in the Channel of 4H-SiC Lateral MOSFETs
| British Library Online Contents | 2013
Strained Si engineering for nanoscale MOSFETs
| British Library Online Contents | 2006
Source engineering in short channel double gate vertical SiGe-MOSFETs
| British Library Online Contents | 2005
| British Library Online Contents | 2000