A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
FPGA implementation of Discrete Wavelet Transform using Distributed Arithmetic Architecture
Discrete Wavelet Transform (DWT) is used in signal compression and enhancement applications. DWT could be implemented using recursive Finite Impulse Response (FIR) filtering. DWT is a very effective analysis tool for many practical applications. Due to computational intensive nature because of multiply operations being a part of, real time processing of signals is being a tough task, as the implementations are not optimized. This paper describes implementation of DWT using Distributed Arithmetic Architecture (DAA) on FPGA device and a novel idea for implementation of Decimator function. The Low Pass FIR filters (LPF) and High Pass FIR filters (HPF) used in DWT are implemented using DAA. Simulations and syntheses are done with Virtex-5 XC5VLX20T-2FF323 FPGA device environment. Conventional Multiplier Architecture (CMA) based DWT system makes use of 8 high-cost resource DSP48Es for use of 8 8X8-bit multipliers, whereas DAA based DWT system makes use of only LUT slices. With CMA design, the maximum throughput achieved by the system is 1009.72Mbit/s, whereas DAA based system provides a throughput of 301.761Mbit/s, a metric which restricts DAA based DWT to low speed applications.
FPGA implementation of Discrete Wavelet Transform using Distributed Arithmetic Architecture
Discrete Wavelet Transform (DWT) is used in signal compression and enhancement applications. DWT could be implemented using recursive Finite Impulse Response (FIR) filtering. DWT is a very effective analysis tool for many practical applications. Due to computational intensive nature because of multiply operations being a part of, real time processing of signals is being a tough task, as the implementations are not optimized. This paper describes implementation of DWT using Distributed Arithmetic Architecture (DAA) on FPGA device and a novel idea for implementation of Decimator function. The Low Pass FIR filters (LPF) and High Pass FIR filters (HPF) used in DWT are implemented using DAA. Simulations and syntheses are done with Virtex-5 XC5VLX20T-2FF323 FPGA device environment. Conventional Multiplier Architecture (CMA) based DWT system makes use of 8 high-cost resource DSP48Es for use of 8 8X8-bit multipliers, whereas DAA based DWT system makes use of only LUT slices. With CMA design, the maximum throughput achieved by the system is 1009.72Mbit/s, whereas DAA based system provides a throughput of 301.761Mbit/s, a metric which restricts DAA based DWT to low speed applications.
FPGA implementation of Discrete Wavelet Transform using Distributed Arithmetic Architecture
Avinash, C.S. (author) / Alex, John Sahaya Rani (author)
2015-05-01
462319 byte
Conference paper
Electronic Resource
English
Fatigue Data Analysis Using Continuous Wavelet Transform and Discrete Wavelet Transform
| British Library Online Contents | 2011
Discrete wavelet transform and seismological signals
| British Library Conference Proceedings | 1997
High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure
| BASE | 2009
Denoising of GPR B-scan images using discrete wavelet transform
| British Library Conference Proceedings | 2023
Improvement of Offline Signature Verification Method Using Discrete Wavelet Transform
| Springer Verlag | 2021