Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Temperature scaling for 35nm gate length high-performance CMOS
Temperature scaling for 35nm gate length high-performance CMOS
Temperature scaling for 35nm gate length high-performance CMOS
Feudel, T. (Autor:in) / Horstmann, M. (Autor:in) / Gerhardt, M. (Autor:in) / Herden, M. (Autor:in) / Herrmann, L. (Autor:in) / Gehre, D. (Autor:in) / Krueger, C. (Autor:in) / Greenlaw, D. (Autor:in) / Raab, M. (Autor:in)
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING ; 7 ; 369-374
01.01.2004
6 pages
Aufsatz (Zeitschrift)
Englisch
DDC:
621.38152
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
British Library Online Contents | 2004
|British Library Online Contents | 2014
|Sub-50nm gate length SOI transistor development for high performance microprocessors
British Library Online Contents | 2004
|Nanotube electronics beyond the CMOS-scaling
IEEE | 2006
|Nano-CMOS scaling: Novel devices and materials
IEEE | 2006
|