A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
Temperature scaling for 35nm gate length high-performance CMOS
Temperature scaling for 35nm gate length high-performance CMOS
Temperature scaling for 35nm gate length high-performance CMOS
Feudel, T. (author) / Horstmann, M. (author) / Gerhardt, M. (author) / Herden, M. (author) / Herrmann, L. (author) / Gehre, D. (author) / Krueger, C. (author) / Greenlaw, D. (author) / Raab, M. (author)
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING ; 7 ; 369-374
2004-01-01
6 pages
Article (Journal)
English
DDC:
621.38152
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
| British Library Online Contents | 2004
| British Library Online Contents | 2014
Sub-50nm gate length SOI transistor development for high performance microprocessors
| British Library Online Contents | 2004
Nanotube electronics beyond the CMOS-scaling
| IEEE | 2006
Nano-CMOS scaling: Novel devices and materials
| IEEE | 2006