Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor
Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor
Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor
Berry, O. (Autor:in) / Hamieh, Y. (Autor:in) / Rael, S. (Autor:in) / Meibody-Tabar, F. (Autor:in) / Vieillard, S. (Autor:in) / Bergogne, D. (Autor:in) / Morel, H. (Autor:in) / Bauer, A.J. / Friedrichs, P. / Krieger, M.
01.01.2010
4 pages
Aufsatz (Zeitschrift)
Englisch
DDC:
620.11
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
A 600V Deep-Implanted Gate Vertical JFET
British Library Online Contents | 2004
|Numerical simulation of implanted top-gate 6H-SiC JFET characteristics
British Library Online Contents | 1999
|