Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET): Fid-Bau Portal

Fachinformationsdienst BAUdigital

Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik

Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET)

Sahoo, S. / Panda, S. / Mishra, G. P. / Dash, S.

This paper presents a 2D analytical model for symmetric double gate Tunnel Field Effect transistor (DG-TFET) based on tunneling path in the channel. The potential profile is obtained by solving 2D Poisson's equation in the rectangular coordinate system. The drain current is extracted by integrating the band to band tunneling generation rate, initial and final tunneling length. The primary focus is on initial tunneling length as it directly influence the drain current amplitude of the device. The DG-TFET shows ON-current improvement as compared with SG-TFET. The validation of analytical results with simulated results is done by TCAD device simulator.

Zugriff

Zugriff prüfen

Verfügbarkeit in meiner Bibliothek prüfen

Bestellung bei Subito €

Seitennavigation

Dokumentinformationen

Ähnliche Titel

Exportieren, teilen und zitieren

Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET)

Sahoo, S. / Panda, S. / Mishra, G. P. / Dash, S.

This paper presents a 2D analytical model for symmetric double gate Tunnel Field Effect transistor (DG-TFET) based on tunneling path in the channel. The potential profile is obtained by solving 2D Poisson's equation in the rectangular coordinate system. The drain current is extracted by integrating the band to band tunneling generation rate, initial and final tunneling length. The primary focus is on initial tunneling length as it directly influence the drain current amplitude of the device. The DG-TFET shows ON-current improvement as compared with SG-TFET. The validation of analytical results with simulated results is done by TCAD device simulator.

Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET)

Sahoo, S. / Panda, S. / Mishra, G. P. / Dash, S.

This paper presents a 2D analytical model for symmetric double gate Tunnel Field Effect transistor (DG-TFET) based on tunneling path in the channel. The potential profile is obtained by solving 2D Poisson's equation in the rectangular coordinate system. The drain current is extracted by integrating the band to band tunneling generation rate, initial and final tunneling length. The primary focus is on initial tunneling length as it directly influence the drain current amplitude of the device. The DG-TFET shows ON-current improvement as compared with SG-TFET. The validation of analytical results with simulated results is done by TCAD device simulator.

Zugriff

Zugriff prüfen

Verfügbarkeit in meiner Bibliothek prüfen

Bestellung bei Subito €

Seitennavigation

Dokumentinformationen

Ähnliche Titel

Exportieren, teilen und zitieren

Dokumentinformationen

Titel:

Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET)

Beteiligte:

Sahoo, S. (Autor:in) / Panda, S. (Autor:in) / Mishra, G. P. (Autor:in) / Dash, S. (Autor:in)

Erschienen in:

2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES) ; 337-341

Erscheinungsdatum:

01.03.2016

Format / Umfang:

407183 byte

ISBN:

978-1-5090-2118-5

DOI:

https://doi.org/10.1109/ICETEESES.2016.7581405

Medientyp:

Aufsatz (Konferenz)

Format:

Elektronische Ressource

Sprache:

Englisch

Ähnliche Titel

Tunneling current characteristics by Al+N isoelectronic traps in Si-TFET; first-principles study

Iizuka, Shota / Asayama, Yoshihiro / Nakayama, Takashi | British Library Online Contents | 2017

Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure

Singh, Balraj / Nath Rai, Trailokya / Gola, Deepti et al. | British Library Online Contents | 2017

Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric

Rahimian, Morteza / Fathipour, Morteza | British Library Online Contents | 2017

Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure

Singh, Balraj / Nath Rai, Trailokya / Gola, Deepti et al. | British Library Online Contents | 2017

Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure

Singh, Balraj / Nath Rai, Trailokya / Gola, Deepti et al. | British Library Online Contents | 2017