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Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor
Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor
Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor
J. Inst. Eng. India Ser. B
Kumar, Manoj (Autor:in)
Journal of The Institution of Engineers (India): Series B ; 104 ; 851-858
01.08.2023
Aufsatz (Zeitschrift)
Elektronische Ressource
Englisch
Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor
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