Fabrication process and properties of InGaAs wires having Si interface control layers for removal of Fermi level pinning: Fid-Bau Portal

Fabrication process and properties of InGaAs wires having Si interface control layers for removal of Fermi level pinning

Fujikura, H. / Tomozawa, H. / Akazawa, M. / Hasegawa, H.

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Fabrication process and properties of InGaAs wires having Si interface control layers for removal of Fermi level pinning

Fujikura, H. / Tomozawa, H. / Akazawa, M. / Hasegawa, H.

Fabrication process and properties of InGaAs wires having Si interface control layers for removal of Fermi level pinning

Fujikura, H. / Tomozawa, H. / Akazawa, M. / Hasegawa, H.

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Check availability in my library

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Document information

Title:

Fabrication process and properties of InGaAs wires having Si interface control layers for removal of Fermi level pinning

Contributors:

Fujikura, H. (author) / Tomozawa, H. (author) / Akazawa, M. (author) / Hasegawa, H. (author)

Published in:

APPLIED SURFACE SCIENCE ; 60 ; 702

Publication date:

1992-01-01

Size:

702 pages

ISSN:

0169-4332

Type of media:

Article (Journal)

Type of material:

Language:

Unknown

Classification:

DDC: 621.35

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