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    Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

    New search for: Le, G.
    New search for: Gao, J.L.
    New search for: Chu, J.K.

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    Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

    New search for: Le, G.
    New search for: Gao, J.L.
    New search for: Chu, J.K.

    Access

    Access via TIB
    Check availability in my library
    Order at Subito €

    Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

    New search for: Le, G.
    New search for: Gao, J.L.
    New search for: Chu, J.K.

    Access

    Access via TIB
    Check availability in my library
    Order at Subito €

    Access

    Access via TIB
    Check availability in my library
    Order at Subito €

    Page navigation

    Document information
    Similar titles

    Export, share and cite

    Document information
    Title:

    Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels

    Contributors:

    Le, G. (author) / Gao, J.L. (author) / Chu, J.K. (author)

    Published in:

    KEY ENGINEERING MATERIALS ; 483 ; 38-42

    Publication date:

    2011-01-01

    Size:

    5 pages

    ISSN:

    1013-9826

    Type of media:

    Article (Journal)

    Type of material:

    Print

    Language:

    English

    Classification:

    DDC:  620.11

    © Metadata Copyright the British Library Board and other contributors. All rights reserved.

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