Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield: Fid-Bau Portal

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Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Koji Sakui / Yisuo Li / Masakazu Kakumu / Kenichi Kanazawa / Iwao Kunishima / Yoshihisa Iwata / Nozomu Harada

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

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Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Koji Sakui / Yisuo Li / Masakazu Kakumu / Kenichi Kanazawa / Iwao Kunishima / Yoshihisa Iwata / Nozomu Harada

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Koji Sakui / Yisuo Li / Masakazu Kakumu / Kenichi Kanazawa / Iwao Kunishima / Yoshihisa Iwata / Nozomu Harada

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

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Title:

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Contributors:

Koji Sakui (author) / Yisuo Li (author) / Masakazu Kakumu (author) / Kenichi Kanazawa (author) / Iwao Kunishima (author) / Yoshihisa Iwata (author) / Nozomu Harada (author)

Published in:

Memories - Materials, Devices, Circuits and Systems, Vol 4, Iss , Pp 100054- (2023)

Publication date:

2023

ISSN:

DOI:

https://doi.org/10.1016/j.memori.2023.100054

Type of media:

Article (Journal)

Type of material:

Electronic Resource

Language:

Unknown

Keywords:

Surrounding Gate Transistor (SGT) , GAA , FinFET , SOI , 1T-DRAM , Capacitorless DRAM , Electric apparatus and materials. Electric circuits. Electric networks , TK452-454.4 , Computer engineering. Computer hardware , TK7885-7895

Metadata by DOAJ is licensed under CC BY-SA 1.0

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