A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
SUBSTRATE FOR POWER MODULE AND MANUFACTURING METHOD THEREFOR
To provide a power-module substrate and a manufacturing method thereof in which small voids are reduced at a bonded part and separation can be prevented. Bonding a metal plate of aluminum or aluminum alloy to at least one surface of a ceramic substrate by brazing, when a cross section of the metal plate is observed by a scanning electron microscope in a field of 3000 magnifications in a depth extent of 5 µm from a bonded interface between the metal plate and the ceramic substrate in a width area of 200 µm from a side edge of the metal plate, residual-continuous oxide existing continuously by 2 µm or more along the bonded interface has total length of 70% or less with respect to a length of the field.
SUBSTRATE FOR POWER MODULE AND MANUFACTURING METHOD THEREFOR
To provide a power-module substrate and a manufacturing method thereof in which small voids are reduced at a bonded part and separation can be prevented. Bonding a metal plate of aluminum or aluminum alloy to at least one surface of a ceramic substrate by brazing, when a cross section of the metal plate is observed by a scanning electron microscope in a field of 3000 magnifications in a depth extent of 5 µm from a bonded interface between the metal plate and the ceramic substrate in a width area of 200 µm from a side edge of the metal plate, residual-continuous oxide existing continuously by 2 µm or more along the bonded interface has total length of 70% or less with respect to a length of the field.
SUBSTRATE FOR POWER MODULE AND MANUFACTURING METHOD THEREFOR
SUBSTRAT FÜR LEISTUNGSMODUL UND HERSTELLUNGSVERFAHREN DAFÜR
SUBSTRAT POUR MODULE DE PUISSANCE, ET PROCÉDÉ DE FABRICATION ASSOCIÉ
NAGASE TOSHIYUKI (author) / KITAHARA TAKESHI (author) / MURANAKA RYO (author)
2021-12-22
Patent
Electronic Resource
English
IPC:
H01L
Halbleiterbauelemente
,
SEMICONDUCTOR DEVICES
/
B32B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
,
Schichtkörper, d.h. aus Ebenen oder gewölbten Schichten, z.B. mit zell- oder wabenförmiger Form, aufgebaute Erzeugnisse
/
C04B
Kalk
,
LIME
/
H05K
PRINTED CIRCUITS
,
Gedruckte Schaltungen
| European Patent Office | 2022
| European Patent Office | 2015
| European Patent Office | 2021
| European Patent Office | 2017