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Retention characteristics of Ge-nanocrystal nonvolatile MOS memories
Nonvolatile memory characteristics on metal-oxidesemiconductor (MOS) structures containing Ge nanocrystals (NCs) produced by ion-implantation and annealing has been investigated. Ge nc MOS which is of interest for application as nonvolatile memory (NVM) was fabricated in an oxide of 35 nm thickness by ion implantation of Ge-ions with the energy of 15 keV and the dose of up to 1×1016 cm−2 followed by rapid thermal annealing at 950 °C for 10 min. The structures have Ge NCs of 3 – 4 nm diameter and 2×1012 cm−2 density. They are located around 5 nm from the interface and are shown to have the capacitance-voltage hysteresis of about 3∼20 V. Charge traps and interface states due to Ge lead to a strong influence on the large C-V hysteresis. High-temperature data-retention analysis shows that according to our extrapolation, the programmed and erased window is reduced by 25% after ten years. Deep level transient spectroscopy (DLTS) and optical DLTS verify the existence of interface states and new charge traps due to Ge NCs in MOS structures. As the Ge dose increases, charge traps and interface states increase. It is suggested that the memory effect is a consequence of charge trapping in the Ge NCs as well as the Si/SiO2 interface states.
Retention characteristics of Ge-nanocrystal nonvolatile MOS memories
Nonvolatile memory characteristics on metal-oxidesemiconductor (MOS) structures containing Ge nanocrystals (NCs) produced by ion-implantation and annealing has been investigated. Ge nc MOS which is of interest for application as nonvolatile memory (NVM) was fabricated in an oxide of 35 nm thickness by ion implantation of Ge-ions with the energy of 15 keV and the dose of up to 1×1016 cm−2 followed by rapid thermal annealing at 950 °C for 10 min. The structures have Ge NCs of 3 – 4 nm diameter and 2×1012 cm−2 density. They are located around 5 nm from the interface and are shown to have the capacitance-voltage hysteresis of about 3∼20 V. Charge traps and interface states due to Ge lead to a strong influence on the large C-V hysteresis. High-temperature data-retention analysis shows that according to our extrapolation, the programmed and erased window is reduced by 25% after ten years. Deep level transient spectroscopy (DLTS) and optical DLTS verify the existence of interface states and new charge traps due to Ge NCs in MOS structures. As the Ge dose increases, charge traps and interface states increase. It is suggested that the memory effect is a consequence of charge trapping in the Ge NCs as well as the Si/SiO2 interface states.
Retention characteristics of Ge-nanocrystal nonvolatile MOS memories
Oh, J.S. (author) / Oh, H.T. (author) / Lee, Y.H. (author) / Yang, W.-C. (author) / Cho, H.Y. (author) / Choi, S.-H. (author) / Park, C.J. (author) / Kim, C.-W. (author)
2006-10-01
377529 byte
Conference paper
Electronic Resource
English
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