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Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies

Yang, G. / Wang, Z. / Kang, S.-M.

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Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies

Yang, G. / Wang, Z. / Kang, S.-M.

Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies

Yang, G. / Wang, Z. / Kang, S.-M.

Access

Access via TIB

Check availability in my library

Order at Subito €

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Document information

Similar titles

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Document information

Title:

Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies

Contributors:

Yang, G. (author) / Wang, Z. (author) / Kang, S.-M. (author)

Published in:

SMART MATERIALS AND STRUCTURES ; 15 ; S21-S28

Publication date:

2006-01-01

Size:

S21-S28

ISSN:

0964-1726

Type of media:

Article (Journal)

Type of material:

Language:

English

Classification:

DDC: 530

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