A platform for research: civil engineering, architecture and urbanism
Gate stack technology for nanoscale devices
The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Sibased devices.
Gate stack technology for nanoscale devices
The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Sibased devices.
Gate stack technology for nanoscale devices
Byoung Hun Lee, (author) / Paul Kirsch, (author) / Seungchul Song, (author) / Rino Choi, (author) / Rajarao Jammy, (author)
2006-10-01
457168 byte
Conference paper
Electronic Resource
English
Gate stack technology for nanoscale devices
British Library Online Contents | 2006
|Ultra-thin parylene used as a gate insulator in nanoscale devices
British Library Online Contents | 2018
|Heavy Water in Gate Stack Processing
British Library Online Contents | 2008
|Issues in High-kappa Gate Stack Interfaces
British Library Online Contents | 2002
|Self-forming nanoscale devices
British Library Online Contents | 2003
|