Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Eine Plattform für die Wissenschaft: Bauingenieurwesen, Architektur und Urbanistik
Gate stack technology for nanoscale devices
The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Sibased devices.
Gate stack technology for nanoscale devices
The historical evolution of gate stack technology for silicon devices is reviewed to provide insight on the challenges in this technology for scaled nanoscale CMOS devices and non-Sibased devices.
Gate stack technology for nanoscale devices
Byoung Hun Lee, (Autor:in) / Paul Kirsch, (Autor:in) / Seungchul Song, (Autor:in) / Rino Choi, (Autor:in) / Rajarao Jammy, (Autor:in)
01.10.2006
457168 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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