A platform for research: civil engineering, architecture and urbanism
A platform for research: civil engineering, architecture and urbanism
Electromigration Modeling at Circuit Layout Level
Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional
Electromigration Modeling at Circuit Layout Level
Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional
Electromigration Modeling at Circuit Layout Level
Tan, Cher Ming (author) / He, Feifei
2013
IX, 103 p. 75 illus., 2 illus. in color
Description based upon print version of record
Book
Electronic Resource
English
DDC:
658.56
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