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Circuit Modeling of Vertical Buried-Grid SiC JFETs

Tolstoy, G. / Peftitsis, D. / Lim, J.K. / Bakowski, M. / Nee, H.P.

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Circuit Modeling of Vertical Buried-Grid SiC JFETs

Tolstoy, G. / Peftitsis, D. / Lim, J.K. / Bakowski, M. / Nee, H.P.

Circuit Modeling of Vertical Buried-Grid SiC JFETs

Tolstoy, G. / Peftitsis, D. / Lim, J.K. / Bakowski, M. / Nee, H.P.

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Access via TIB

Check availability in my library

Order at Subito €

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Document information

Title:

Circuit Modeling of Vertical Buried-Grid SiC JFETs

Contributors:

Tolstoy, G. (author) / Peftitsis, D. (author) / Lim, J.K. (author) / Bakowski, M. (author) / Nee, H.P. (author) / Bauer, A.J. / Friedrichs, P. / Krieger, M. / Pensl, G. / Rupp, R.

Published in:

Silicon Carbide and Related Materials 2009 ; 965-968

MATERIALS SCIENCE FORUM ; 645/648

Publication date:

2010-01-01

Size:

4 pages

ISSN:

0255-5476

Type of media:

Article (Journal)

Type of material:

Language:

English

Classification:

DDC: 620.11

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