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Hot carrier stress in 70-nm nMOSFET with various bias conditions
This study presents a 70-nm nMOSFET degradation by hot carrier stress. The DC performance drifts of the device due to hot carrier stress are examined experimentally before and after stress for a 70-nm nMOSFET. Although the substrate current of a 70-nm nMOSFET has different characteristics from that of a long channel device, it can be a good indicator of hot carrier stress. The industrial practice to estimate the device lifetime using the measured lifetime versus 1/VDS plot cannot be applied to a 70-nm nMOSFET, but the method using the substrate current is useful to for this application.
Hot carrier stress in 70-nm nMOSFET with various bias conditions
This study presents a 70-nm nMOSFET degradation by hot carrier stress. The DC performance drifts of the device due to hot carrier stress are examined experimentally before and after stress for a 70-nm nMOSFET. Although the substrate current of a 70-nm nMOSFET has different characteristics from that of a long channel device, it can be a good indicator of hot carrier stress. The industrial practice to estimate the device lifetime using the measured lifetime versus 1/VDS plot cannot be applied to a 70-nm nMOSFET, but the method using the substrate current is useful to for this application.
Hot carrier stress in 70-nm nMOSFET with various bias conditions
Hyun-Sik Choi, (author) / Seung-Ho Hong, (author) / Hee-Sung Kang, (author) / Yoon-Ha Jeong, (author)
2006-10-01
255624 byte
Conference paper
Electronic Resource
English
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